/******************************************
    ** (C)Copyright by N.T.T 1993(unpublished) 
    ** All rights are reserved.                
    ******************************************/
    /*-----------------------------------------------------------------------*/
    /*includes  from PARTHENON system library                                */
    /*-----------------------------------------------------------------------*/
  8 %i <r256_8.h>  /*8-bit SRAM memory*/
  9 %i <inc8.h>    /*8-bit incrementor*/
 10 %i <cla8.h>    /*8-bit carry look-ahead adder*/
 11 
    /*-----------------------------------------------------------------------*/
    /*defines                                                                */
    /*-----------------------------------------------------------------------*/
 15 %d LDAI 0x80    /* a <- op2 */
 16 %d LDAX 0x01    /* a <- (x) */
 17 %d STAX 0x02    /* (x) <- a */
 18 %d LDXI 0x83    /* x <- op2 */
 19 %d LDXM 0x84    /* x <- (op2) */
 20 %d STXM 0x85    /* (op2) <- x */
 21 %d INX  0x06    /* x <- x + 1 */
 22 %d SEC  0x07    /* c <- 1 */
 23 %d CLC  0x08    /* c <- 0 */
 24 %d ROLA 0x09    /* c || a <- a || c */
 25 %d COMA 0x0a    /* a <- ^ a */
 26 %d ADCX 0x0b    /* a <- a + (x) + c */
 27 %d ANDX 0x0c    /* a <- a & (x) */
 28 %d BC   0x8d    /* if (c) pc <- op2 */
 29 %d IN   0x0e    /* a <- dti */
 30 %d OUT  0x0f    /* dto <- a */
 31 
    /*-----------------------------------------------------------------------*/
    /*interface declaration of 8-bit cpu                                     */
    /*-----------------------------------------------------------------------*/
 35 declare cpu {
 36   input    dti<8>;
 37   output   dto<8>;
 38   output   adrs<8>;
 39   instrout memory_read;
 40   instrout memory_write;
 41   instrin  start;
 42 }/*cpu*/
 43 
    /*-----------------------------------------------------------------------*/
    /*module definition of top                                               */
    /*-----------------------------------------------------------------------*/
 47 module top {
 48   instrin   start;
 49   cpu       cpu;
 50   r256_8    ram;
 51 
 52   instruct start cpu.start();
 53   instruct cpu.memory_read cpu.dti= ram.read(cpu.adrs).dout;
 54   instruct cpu.memory_write ram.write(cpu.adrs,cpu.dto);
 55 }/*top*/
 56 
    /*-----------------------------------------------------------------------*/
    /*module definition of 8-bit cpu                                         */
    /*-----------------------------------------------------------------------*/
 60 module cpu {
 61   input    dti<8>;
 62   output   dto<8>;
 63   output   adrs<8>;
 64   instrout memory_read;
 65   instrout memory_write;
 66   instrin  start;
 67 
 68   reg_wr   pc<8>;
 69   reg      a<8>;
 70   reg      x<8>;
 71   reg      c;
 72   reg      op1<8>;
 73   reg      op2<8>;
 74   reg      md<8>;
 75   inc8     inc;
 76   cla8     cla;
 77 
 78   instr_arg memory_read(adrs);
 79   instr_arg memory_write(adrs,dto);
 80 
 81   stage_name if {
 82     task ift();
 83   }
 84   stage_name exec {
 85     task ext();
 86   }
 87 
 88   instruct start generate if.ift();
 89 
 90   stage if {
 91     state_name  fetch1;
 92     state_name  fetch2;
 93     first_state fetch1;
 94 
 95     state fetch1 par {
 96       op1:= memory_read(pc).dti;
 97       pc:= inc.do(pc).out;
 98       any {
 99         dti<7>: goto fetch2;
100         else  : relay exec.ext();    /*relay= finish and generate*/
101       }
102     }/*fetch1*/
103 
104     state fetch2 par {
105       op2:= memory_read(pc).dti;
106       pc:= inc.do(pc).out;
107       goto fetch1;
108       relay exec.ext();
109     }/*fetch1*/
110   }/*if*/
111 
112   stage exec {
113     state_name  exec1;
114     state_name  exec2;
115     first_state exec1;
116 
117     state exec1 any {
118       (op1== ADCX) | (op1== ANDX): par {
119         md:= memory_read(x).dti;
120         goto exec2;
121         generate if.ift();
122       }
123       else: par {
124         any {
125           op1== LDAI     : a:= op2;
126           op1== LDAX     : a:= memory_read(x).dti;
127           op1== STAX     : memory_write(x,a);
128           op1== LDXI     : x:= op2;
129           op1== LDXM     : x:= memory_read(op2).dti;
130           op1== STXM     : memory_write(op2,x);
131           op1== INX      : x:= cla.do(0b1,x,0x00).out;
132           op1== SEC      : c:= 0b1;
133           op1== CLC      : c:= 0b0;
134           op1== ROLA     : par { a:= (a || c)<7:0>; c:= a<7>; }
135           op1== COMA     : a:= ^a;
136           (op1== BC) & c : pc:= op2;
137           op1== IN       : a:= dti;
138           op1== OUT      : dto= a;
139         }
140         relay if.ift();
141       }
142     }/*exec1*/
143 
144     state exec2 par {
145       any {
146         op1== ADCX: a:= cla.do(c,a,md).out;
147         op1== ANDX: a:= a & md;
148       }
149       goto exec1;
150       finish;
151     }/*exec2*/
152   }/*exec*/
153 }/*cpu*/