/*  $RCSfile:$ */
/*  $Author:$ */
/*  $Date:$ */
/*  $Revision:$ */
/*  $State:$ */
declare memunit {
  input i;
  output o;
  instrin do;
  input rn_we;
  input adr<16>;
  instr_arg do( rn_we, adr, i );
}
circuit memunit {
  input i;
  output o;
  instrin do;
  input rn_we;
  input adr<16>;
  
  mem m[65536];

  instruct  do  any { rn_we  : m[adr]  :=  i;  ^rn_we : o  =  m[adr]; }
}
/*  $RCSfile:$ */
/*  $Author:$ */
/*  $Date:$ */
/*  $Revision:$ */
/*  $State:$ */
declare memory_module {
  input  i0,  i1,  i2,  i3,  i4,  i5,  i6,  i7;
  input  i8,  i9, i10, i11, i12, i13, i14, i15;
  input i16, i17, i18, i19, i20, i21, i22, i23;
  input i24, i25, i26, i27, i28, i29, i30, i31;

  output  o0,  o1,  o2,  o3,  o4,  o5,  o6,  o7;
  output  o8,  o9, o10, o11, o12, o13, o14, o15;
  output o16, o17, o18, o19, o20, o21, o22, o23;
  output o24, o25, o26, o27, o28, o29, o30, o31;

  instrin  do0,  do1,  do2,  do3,  do4,  do5,  do6,  do7;
  instrin  do8,  do9, do10, do11, do12, do13, do14, do15;
  instrin do16, do17, do18, do19, do20, do21, do22, do23;
  instrin do24, do25, do26, do27, do28, do29, do30, do31;
  instrin complete;

  input  rn_we0,  rn_we1,  rn_we2,  rn_we3,  rn_we4,  rn_we5,  rn_we6,  rn_we7;
  input  rn_we8,  rn_we9, rn_we10, rn_we11, rn_we12, rn_we13, rn_we14, rn_we15;
  input rn_we16, rn_we17, rn_we18, rn_we19, rn_we20, rn_we21, rn_we22, rn_we23;
  input rn_we24, rn_we25, rn_we26, rn_we27, rn_we28, rn_we29, rn_we30, rn_we31;

  input  adr0<16>,  adr1<16>,  adr2<16>,  adr3<16>;
  input  adr4<16>,  adr5<16>,  adr6<16>,  adr7<16>;
  input  adr8<16>,  adr9<16>, adr10<16>, adr11<16>;
  input adr12<16>, adr13<16>, adr14<16>, adr15<16>;
  input adr16<16>, adr17<16>, adr18<16>, adr19<16>;
  input adr20<16>, adr21<16>, adr22<16>, adr23<16>;
  input adr24<16>, adr25<16>, adr26<16>, adr27<16>;
  input adr28<16>, adr29<16>, adr30<16>, adr31<16>;
  
  instr_arg  do0(  rn_we0,  adr0,  i0); instr_arg  do1(  rn_we1,  adr1,	 i1);
  instr_arg  do2(  rn_we2,  adr2,  i2); instr_arg  do3(  rn_we3,  adr3,  i3);
  instr_arg  do4(  rn_we4,  adr4,  i4); instr_arg  do5(  rn_we5,  adr5,  i5);
  instr_arg  do6(  rn_we6,  adr6,  i6); instr_arg  do7(  rn_we7,  adr7,  i7);
  instr_arg  do8(  rn_we8,  adr8,  i8); instr_arg  do9(  rn_we9,  adr9,  i9);
  instr_arg do10( rn_we10, adr10, i10); instr_arg do11( rn_we11, adr11, i11);
  instr_arg do12( rn_we12, adr12, i12); instr_arg do13( rn_we13, adr13, i13);
  instr_arg do14( rn_we14, adr14, i14); instr_arg do15( rn_we15, adr15, i15);
  instr_arg do16( rn_we16, adr16, i16); instr_arg do17( rn_we17, adr17, i17); 
  instr_arg do18( rn_we18, adr18, i18); instr_arg do19( rn_we19, adr19, i19);
  instr_arg do20( rn_we20, adr20, i20); instr_arg do21( rn_we21, adr21, i21); 
  instr_arg do22( rn_we22, adr22, i22); instr_arg do23( rn_we23, adr23, i23); 
  instr_arg do24( rn_we24, adr24, i24); instr_arg do25( rn_we25, adr25, i25); 
  instr_arg do26( rn_we26, adr26, i26); instr_arg do27( rn_we27, adr27, i27); 
  instr_arg do28( rn_we28, adr28, i28); instr_arg do29( rn_we29, adr29, i29);
  instr_arg do30( rn_we30, adr30, i30); instr_arg do31( rn_we31, adr31, i31); 

}
/*  $RCSfile:$ */
/*  $Author:$ */
/*  $Date:$ */
/*  $Revision:$ */
/*  $State:$ */
%i "memunit.h"

module memmod {
  input  i0,  i1,  i2,  i3,  i4,  i5,  i6,  i7;
  input  i8,  i9, i10, i11, i12, i13, i14, i15;
  input i16, i17, i18, i19, i20, i21, i22, i23;
  input i24, i25, i26, i27, i28, i29, i30, i31;

  output  o0,  o1,  o2,  o3,  o4,  o5,  o6,  o7;
  output  o8,  o9, o10, o11, o12, o13, o14, o15;
  output o16, o17, o18, o19, o20, o21, o22, o23;
  output o24, o25, o26, o27, o28, o29, o30, o31;

  instrin  do0,  do1,  do2,  do3,  do4,  do5,  do6,  do7;
  instrin  do8,  do9, do10, do11, do12, do13, do14, do15;
  instrin do16, do17, do18, do19, do20, do21, do22, do23;
  instrin do24, do25, do26, do27, do28, do29, do30, do31;
  instrin complete;
  
  input  rn_we0,  rn_we1,  rn_we2,  rn_we3,  rn_we4,  rn_we5,  rn_we6,  rn_we7;
  input  rn_we8,  rn_we9, rn_we10, rn_we11, rn_we12, rn_we13, rn_we14, rn_we15;
  input rn_we16, rn_we17, rn_we18, rn_we19, rn_we20, rn_we21, rn_we22, rn_we23;
  input rn_we24, rn_we25, rn_we26, rn_we27, rn_we28, rn_we29, rn_we30, rn_we31;

  input  adr0<16>,  adr1<16>,  adr2<16>,  adr3<16>;
  input  adr4<16>,  adr5<16>,  adr6<16>,  adr7<16>;
  input  adr8<16>,  adr9<16>, adr10<16>, adr11<16>;
  input adr12<16>, adr13<16>, adr14<16>, adr15<16>;
  input adr16<16>, adr17<16>, adr18<16>, adr19<16>;
  input adr20<16>, adr21<16>, adr22<16>, adr23<16>;
  input adr24<16>, adr25<16>, adr26<16>, adr27<16>;
  input adr28<16>, adr29<16>, adr30<16>, adr31<16>;

  sel   stop;
  memunit munit0, munit1, munit2, munit3, munit4, munit5, munit6, munit7 ;
  memunit munit8, munit9, munit10, munit11, munit12, munit13, munit14, munit15;
  memunit munit16, munit17, munit18, munit19, munit20, munit21, munit22, munit23 ;
  memunit munit24, munit25, munit26, munit27, munit28, munit29, munit30, munit31;

  par {
    stop = 0b0;
    any {
      ^do0 : munit0.do(0b0, 0x0000, 0b0);
      ^do1 : munit1.do(0b0, 0x0000, 0b0);
      ^do2 : munit2.do(0b0, 0x0000, 0b0);
      ^do3 : munit3.do(0b0, 0x0000, 0b0);
      ^do4 : munit4.do(0b0, 0x0000, 0b0);
      ^do5 : munit5.do(0b0, 0x0000, 0b0);
      ^do6 : munit6.do(0b0, 0x0000, 0b0);
      ^do7 : munit7.do(0b0, 0x0000, 0b0);
      ^do8 : munit8.do(0b0, 0x0000, 0b0);
      ^do9 : munit9.do(0b0, 0x0000, 0b0);
      ^do10: munit10.do(0b0, 0x0000, 0b0);
      ^do11: munit11.do(0b0, 0x0000, 0b0);
      ^do12: munit12.do(0b0, 0x0000, 0b0);
      ^do13: munit13.do(0b0, 0x0000, 0b0);
      ^do14: munit14.do(0b0, 0x0000, 0b0);
      ^do15: munit15.do(0b0, 0x0000, 0b0);
      ^do16: munit16.do(0b0, 0x0000, 0b0);
      ^do17 : munit17.do(0b0, 0x0000, 0b0);
      ^do18 : munit18.do(0b0, 0x0000, 0b0);
      ^do19 : munit19.do(0b0, 0x0000, 0b0);
      ^do20 : munit20.do(0b0, 0x0000, 0b0);
      ^do21 : munit21.do(0b0, 0x0000, 0b0);
      ^do22 : munit22.do(0b0, 0x0000, 0b0);
      ^do23 : munit23.do(0b0, 0x0000, 0b0);
      ^do24 : munit24.do(0b0, 0x0000, 0b0);
      ^do25 : munit25.do(0b0, 0x0000, 0b0);
      ^do26: munit26.do(0b0, 0x0000, 0b0);
      ^do27: munit27.do(0b0, 0x0000, 0b0);
      ^do28: munit28.do(0b0, 0x0000, 0b0);
      ^do29: munit29.do(0b0, 0x0000, 0b0);
      ^do30: munit30.do(0b0, 0x0000, 0b0);
      ^do31: munit31.do(0b0, 0x0000, 0b0);
    }
  }
  instruct  do0  par {
    munit0.do(rn_we0, adr0, i0);
    if ( ^rn_we0 ) o0 = munit0.o;
    }
  instruct  do1  par {
    munit1.do(rn_we1, adr1, i1);
    if ( ^rn_we1 ) o1 = munit1.o;
  }
  instruct  do2  par {
    munit2.do(rn_we2, adr2, i2);
    if ( ^rn_we2 ) o2 = munit2.o;
  }
  instruct  do3  par {
    munit3.do(rn_we3, adr3, i3);
    if ( ^rn_we3 ) o3 = munit3.o;
  }
  instruct  do4  par {
    munit4.do(rn_we4, adr4, i4);
    if ( ^rn_we4 ) o4 = munit4.o;
  }
  instruct  do5  par {
    munit5.do(rn_we5, adr5, i5);
    if ( ^rn_we5 ) o5 = munit5.o;
  }
  instruct  do6  par {
    munit6.do(rn_we6, adr6, i6);
    if ( ^rn_we6 ) o6 = munit6.o;
  }
  instruct  do7  par {
    munit7.do(rn_we7, adr7, i7);
    if ( ^rn_we7 ) o7 = munit7.o;
  }
  instruct  do8  par {
    munit8.do(rn_we8, adr8, i8);
    if ( ^rn_we8 ) o8 = munit8.o;
  }
  instruct  do9  par {
    munit9.do(rn_we9, adr9, i9);
    if ( ^rn_we9 ) o9 = munit9.o;
  }
  instruct  do10  par {
    munit10.do(rn_we10, adr10, i10);
    if ( ^rn_we10 ) o10 = munit10.o;
  }
  instruct  do11  par {
    munit11.do(rn_we11, adr11, i11);
    if ( ^rn_we11 ) o11 = munit11.o;
  }
  instruct  do12  par {
    munit12.do(rn_we12, adr12, i12);
    if ( ^rn_we12 ) o12 = munit12.o;
  }
  instruct  do13  par {
    munit13.do(rn_we13, adr13, i13);
    if ( ^rn_we13 ) o13 = munit13.o;
  }
  instruct  do14  par {
    munit14.do(rn_we14, adr14, i14);
    if ( ^rn_we14 ) o14 = munit14.o;
  }
  instruct  do15  par {
    munit15.do(rn_we15, adr15, i15);
    if ( ^rn_we15 ) o15 = munit15.o;
  }

  instruct  do16  par {
    munit16.do(rn_we16, adr16, i16);
    if ( ^rn_we16 ) o16 = munit16.o;
  }
  instruct  do17  par {
    munit17.do(rn_we17, adr17, i17);
    if ( ^rn_we17 ) o17 = munit17.o;
  }
  instruct  do18  par {
    munit18.do(rn_we18, adr18, i18);
    if ( ^rn_we18 ) o18 = munit18.o;
  }
  instruct  do19  par {
    munit19.do(rn_we19, adr19, i19);
    if ( ^rn_we19 ) o19 = munit19.o;
  }
  instruct  do20  par {
    munit20.do(rn_we20, adr20, i20);
    if ( ^rn_we20 ) o20 = munit20.o;
  }
  instruct  do21  par {
    munit21.do(rn_we21, adr21, i21);
    if ( ^rn_we21 ) o21 = munit21.o;
  }
  instruct  do22  par {
    munit22.do(rn_we22, adr22, i22);
    if ( ^rn_we22 ) o22 = munit22.o;
  }
  instruct  do23  par {
    munit23.do(rn_we23, adr23, i23);
    if ( ^rn_we23 ) o23 = munit23.o;
  }
  instruct  do24  par {
    munit24.do(rn_we24, adr24, i24);
    if ( ^rn_we24 ) o24 = munit24.o;
  }
  instruct  do25  par {
    munit25.do(rn_we25, adr25, i25);
    if ( ^rn_we25 ) o25 = munit25.o;
  }
  instruct  do26  par {
    munit26.do(rn_we26, adr26, i26);
    if ( ^rn_we26 ) o26 = munit26.o;
  }
  instruct  do27  par {
    munit27.do(rn_we27, adr27, i27);
    if ( ^rn_we27 ) o27 = munit27.o;
  }
  instruct  do28  par {
    munit28.do(rn_we28, adr28, i28);
    if ( ^rn_we28 ) o28 = munit28.o;
  }
  instruct  do29  par {
    munit29.do(rn_we29, adr29, i29);
    if ( ^rn_we29 ) o29 = munit29.o;
  }
  instruct  do30  par {
    munit30.do(rn_we30, adr30, i30);
    if ( ^rn_we30 ) o30 = munit30.o;
  }
  instruct  do31  par {
    munit31.do(rn_we31, adr31, i31);
    if ( ^rn_we31 ) o31 = munit31.o;
  }

  instruct complete stop = 0b1;

}